The code generator does not explicitly group primitive blocks that constitute a nonatomic masked subsystem block in the generated code. This flexibility allows for more efficient code generation. In certain cases, you can achieve grouping by configuring the masked subsystem block to execute as an atomic unit by selecting the治疗作为原子单元option.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
HDL Architecture
This block has a single, default HDL architecture.
HDL Block Properties
ConstrainedOutputPipeline |
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is0 。有关更多详细信息,请参阅ConstrainedOutputPipeline(HDL Coder)。 |
InputPipeline |
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0 。有关更多详细信息,请参阅InputPipeline(HDL Coder)。 |
OutputPipeline |
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0 。有关更多详细信息,请参阅OutputPipeline(HDL Coder)。 |