Documentation

HDL FIFO

Stores sequence of input samples in first in, first out (FIFO) register

Library

HDL Coder / HDL Operations

Description

TheHDL FIFOblock stores a sequence of input samples in a first in, first out (FIFO) register.

HDL Code Generation

For simulation results that match the generated HDL code, in the Solver pane of the Configuration Parameters dialog box, clear the checkbox forTreat each discrete rate as a separate task. When the checkbox is cleared, single-tasking mode is enabled.

If you simulate this block withTreat each discrete rate as a separate taskselected, multitasking mode is enabled. The output data can update in the same cycle but in the generated HDL code, the output data is updated one cycle later.

Parameters

Register size

指定FIFO regist条目的数量er can hold. The minimum is 4. The default is 10.

The ratio of output sample time to input sample time

Inputs (In,Push) and outputs (Out,Pop) can run at different sample times. Enter the ratio of output sample time to input sample time. Use a positive integer or1/N, whereNis a positive integer. The default is 1.

For example:

  • If you enter2, the output sample time is twice the input sample time, meaning the outputs run slower.

  • If you enter1/2, the output sample time is half the input sample time, meaning the outputs run faster.

TheFull,Empty, andNumsignals run at the faster rate.

Push onto full register

Response (Ignore,Error, orWarning) to a trigger received at the Push port when the register is full. The default isWarning.

Pop empty register

Response (Ignore,Error, orWarning) to a trigger received at the Pop port when the register is empty. The default isWarning.

Show empty register indicator port (Empty)

Enable the Empty output port, which is high (1) when the FIFO register is empty and low (0) otherwise.

Show full register indicator port (Full)

Enable the Full output port, which is high (1) when the FIFO register is full and low (0) otherwise.

Show number of register entries port (Num)

Enable the Num output port, which tracks the number of entries currently in the queue.

Ports

The block has the following ports:

In

Data input signal.

Push

Control signal. When this port receives a value of1, the block pushes the input at theInport onto the end of the FIFO register.

Pop

Control signal. When this port receives a value of1, the block pops the first element off the FIFO register and holds theOutport at that value.

Out

Data output signal.

Empty

块FIFO regist时断言这个信号er is empty. This port is optional.

Full

块FIFO regist时断言这个信号er is full. This port is optional.

Num

Current number of data values in the FIFO register. This port is optional.

If two or more of the control input ports are triggered in the same time step, the operations execute in the following order:

  1. Pop

  2. Push

See Also

Introduced in R2014a

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