Documentation

Mux

Combine several input signals into vector (HDL Coder)

Description

The Mux block is available with Simulink^®.

For information about the simulation behavior and block parameters, seeMux.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline: Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See alsoConstrainedOutputPipeline.
InputPipeline: Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See alsoInputPipeline.
OutputPipeline: Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See alsoOutputPipeline.

Complex Data Support

This block supports code generation for complex signals.

Restrictions

Buses are not supported for HDL code generation.

Introduced in R2014a

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