Documentation

Dilation

Morphological dilate of binary pixel data (HDL Coder)

Description

The Dilation block is available with Vision HDL Toolbox™.

For information about the simulation behavior and block parameters, seeDilation.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline: Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. See alsoConstrainedOutputPipeline.
InputPipeline: Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See alsoInputPipeline.
OutputPipeline: Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See alsoOutputPipeline.

Restrictions

You cannot generate HDL for this block inside aResettable Synchronous Subsystem.

Introduced in R2015a

Was this topic helpful?

HDL Coder Documentation

万博1manbetx

Try MATLAB, Simulink, and Other Products