Delay

Delay input signal by fixed or variable sample periods (HDL Coder)

Description

TheDelayblock is available with Simulink^®. For information about simulation behavior and block parameters, seeDelay.

Block Parameter Setting	Description
SetExternal resetto`Level`.	Generates a reset port in the HDL code.
SelectShow enable port.	Generates an enable port in the HDL code.
ForInitial condition, setSourceto`Dialog`and enter the value.	Specifies an initial condition for the block.
SetInput processingto`Columns as channels (frame based)`.	Expects vector input data, where each element of the vector represents a sample in time.

If you use aState Controlblock with theDelayblock inside a subsystem in your Simulink model, use these additional settings.

Block Parameter Setting	Description
SetExternal resetto`Level hold`for`Synchronous`mode and`Level`for`Classic`mode of theState Controlblock.	Generates a reset port in the HDL code.
SetDelay lengthto zero for aDelayblock with an external enable port.	Treated as a wire in only`Synchronous`mode of theState Controlblock.
SetDelay lengthto zero for aDelayblock with an external reset port.	Treated as a wire in`Synchronous`and`Classic`modes of theState Controlblock.

For more information about theState Controlblock, seeState Control.

This block has a single, default HDL architecture.

InputPipeline: Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See alsoInputPipeline.
OutputPipeline: Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. See alsoOutputPipeline.
ResetType: Suppress reset logic generation. The default isdefault, which generates reset logic. See alsoResetType.
UseRAM: Map delays to RAM instead of registers. The default isoff. See alsoUseRAM.

This block supports code generation for complex signals.

ForInitial conditionandDelay length,Sourceset toInput portis not supported for HDL code generation.

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