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Getting Started with MATLAB to HDL Workflow

Basic HDL Code Generation with the Workflow Advisor

Generating Modular Code for Functions

Working with Fixed-Point Code

Generate HDL Code from MATLAB Code Using the Command Line Interface

System Design with HDL Code Generation from MATLAB and Simulink

Float to Fixed Tutorials

Floating-Point to Fixed-Point Conversion

Fixed-Point Type Conversion and Refinement

Working with Generated Fixed-Point Files

Fixed-Point Type Conversion and Derived Ranges

Generate HDL-compatible lookup table function replacements using 'coder.approximate'

Generate HDL code from MATLAB functions using automated lookup table generation

System Objects

HDL Code Generation from System Objects

Model State with Persistent Variables and System Objects

HDL Code Generation from hdl.RAM System Object

HDL Code Generation from A Non-Restoring Square Root System Object

HDL Code Generation from Viterbi Decoder System Object

Optimizations

Distributed Pipelining for Clock Speed Optimization

Map Matrices to Block RAMs to Reduce Area

Resource Sharing of Multipliers to Reduce Area

Loop Streaming to Reduce Area

Constant Multiplier Optimization to Reduce Area

Workflow

Getting Started with FPGA Turnkey Workflow

Signal Processing

LMS Filter: Noise Cancellation

Bisection Algorithm to Calculate Square Root of an Unsigned Fixed-Point Number

Communications

Timing Offset Estimation

Data Packetization

Transmit and Receive FIFO

Image Processing

Accelerate a Pixel-Streaming Design Using MATLAB Coder

Enhanced Edge Detection from Noisy Color Video

Corner Detection

Adaptive Median Filter

Contrast Adjustment

Image Enhancement by Histogram Equalization

Image Format Conversion: RGB to YUV

High Dynamic Range Imaging

Verification

Verify Sobel Edge Detection Algorithm in MATLAB-to-HDL Workflow

Simulink Examples

Modeling

CORDIC Algorithm Using the MATLAB® Function Block

Getting Started with RAM and ROM in Simulink®

硬件设计模式使用the MATLAB Function Block

Using Multiple Clocks in HDL Coder™

Using the State Control block to generate more efficient code with HDL Coder™

Resettable Subsystem Support in HDL Coder™

Optimizations

Use Multicycle Path Constraints to Meet Timing for Slow Paths

Distributed Pipelining: Speed Optimization

Streaming: Area Optimization

Resource Sharing For Area Optimization

Single-rate Resource Sharing Architecture

Delay Balancing and Validation Model Workflow In HDL Coder™

Control the Scope of Delay Balancing

Clock Rate Pipelining

Delay Balancing on multi-rate designs

Workflow

FPGA Floating-Point Library IP Mapping

Using Altera DSP Builder Advanced Blockset with HDL Coder

Using Xilinx System Generator for DSP with HDL Coder

Signal Processing

Generate HDL Code for Programmable FIR Filter

Generate HDL Code for Multichannel FIR Filter

Generate HDL Code for FFT HDL Optimized Block

Generate HDL Code for High Throughput Channelizer

Communications

IEEE 802.11 WLAN - HDL Optimized Beacon Frame Receiver with Captured Data

HDL Optimized QAM Transmitter and Receiver

HDL Implementation of LTE OFDM Modulator and Detector

HDL Optimized QPSK Transmitter

HDL Optimized QPSK Receiver with Captured Data

HDL Code Generation for Viterbi Decoder

Image Processing

Gamma Correction

Histogram Equalization

Edge Detection and Image Overlay

Edge Detection and Image Overlay with Impaired Frame

Noise Removal and Image Sharpening

Multi-Zone Metering

Motor Control

Field-Oriented Control of a Permanent Magnet Synchronous Machine

Verification

HDL Verifier Cosimulation Model Generation in HDL Coder™

Verify HDL Design With Large Data Set Using SystemVerilog DPI Test Bench

Single Precision Floating Point Examples

Single Precision Floating Point Support: Field-Oriented Control Algorithm

Hardware-Software Codesign Workflow Examples

Tutorials

开始使用硬件软件合作设计Workflow for Xilinx Zynq Platform

开始使用硬件软件合作设计Workflow for Intel SoC Devices

Getting Started with the HDL Workflow Command-Line Interface

Save Target Hardware Settings in Model

IP Core Generation Workflow

IP Core Generation Workflow without an Embedded ARM Processor: Xilinx Kintex-7 KC705

IP Core Generation Workflow without an Embedded ARM Processor: Arrow DECA MAX 10 FPGA Evaluation Kit

IP Core Generation Workflow with a MicroBlaze processor: Xilinx Kintex-7 KC705

Using IP Core Generation Workflow from MATLAB: LED Blinking

IP Core Generation of an I2C Controller IP to Configure the Audio Codec Chip.

Application Examples

Running an audio filter on live audio input using a Zynq board

Getting Started with AXI4-Stream Interface in Zynq Workflow

Getting Started with AXI4-Stream Video Interface in Zynq Workflow

Performing Large Matrix Operation on FPGA using External Memory

Custom Reference Design

Authoring a reference design for audio system on a Zynq board

Authoring a reference design for audio system on a ZYBO board

Define and Register Custom Board and Reference Design for Zynq Workflow

Define and Register Custom Board and Reference Design for Intel SoC Workflow

Verification

Debug a Zynq Design Using HDL Coder and Embedded Coder

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